Samstag, 29. Dezember 2012

SVF Interpreter for VHDL Testbench

Digital chips often contain a JTAG port, which is used to implemente boundary scan and to access internal functionality of the chip, like programming and debugging.

One widespread "standard" to specify JTAG operations is SVF (Serial Vector Format). Many tools can generate SVF files which are then used to operate the JTAG signals of a chip, e.g. with Lib(X)SVF.

As everything in chip design, the JTAG functionality also has to be verified during development. At this time, all modules as well as the whole chip are simulated. vhdl-svf provides an SVF interpreter, written in pure VHDL, which reads a SVF file and exercises the JTAG signals. It is inteded to be integrated in a testbench to verify the chip design.

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