Mittwoch, 27. April 2011

EZ-USB AN2131 External Memory Timing

The EZ-USB Technical Reference Manual of the AN2131 and friends shows that all external memory read and write strobe signals are active (low) for two CLK24 cycles (see Fig. 13-1 to 13-4). Important: That this is only true if the wait states are disabled as described in Sec. B.2.2.

After reset the default is one wait state which extends the strobe signals to four CLK24 cycles.

Bits 0 to 2 of the SFR CKCON have to be set to 0 explicitly for zero wait states with a strobe width of two.

Dienstag, 26. April 2011

LPC1102 WL-CSP Images

NXP (former Philips Semiconductor) sent a sample of a LPC1102 ARM Cortex-M0 microcontroller in a tiny 16-pin WL-CSP (wafer-level chip-scale-package). This means that the package has the size of the chip die, or the pure die is used directly. The die is only 2.2x2.3mm with a ball pitch of 0.5mm. At the top of the die solder bumps similiar to a BGA package are used to connect the chip to a PCB.

The first image shows the whole chip (tightly fitting in the microscope's view at a magnification of 2x). The 16 balls are easily visible. At the border of the chip all pads are placed. Only a few of them are connected to the balls via the signal redistribution layer. On some unconnected pads there are scratches from the wafer prober needles during final product test.

At a magnification of 5x the connections of the redistribution layer to the chip pads reveal a nice pit.

At the top right corner a chip label shows that it really is a LPC111XL with just some peripherals not connected to the outer world. It is not sure whether NXP uses fully functional dies and just doesn't tell anybody, or if the product test revealed that these unused peripherals don't work. The latter case is clever, because they can sell chips which would otherwise be rejects.

An even close look at a magnification of 20x shows one wire of the redistribution layer and the underlying semiconductor layers. The following images have three different focus settings. Watch the sharp spots.


There are a lot more colorful places on the chip. These complicated and irregular parts usually are analog peripherals. These are hand crafted by design engineers.

At 50x magnification it is really tedious to find a focus plane. The following images are details of the previous two.

The digital parts are implemented with standard cell libraries of logic gates (AND, OR, D-FF, ...). Automatic tools optimize the placement and routing to connect them. The following image shows a detail of logic structures. In the mostly green area many horizontal connections between the cells are visible. Below these (yellowish) vertical connections are visible. These wires completely cover the actual logic cells below them. At some places filler structures are inserted to avoid areas of too inhomogeneous metal distribution. The two vertical lines at the left might be power distribution at the chip.

Many more images with varying magnifications and focus depths are available in the album.

Invent a Chip

The contest "Invent a Chip" is organized by the Institute of Computer Technology (ICT) at the Vienna University of Technology (TU Wien) and the Österreichischer Verband für Elektrotechnik (OVE). The audience are Austrian pupils in the age of 15-18 years, mainly of electrical and electronics education (HTLs). This year the contest is performed for the first time in Austria, but it is inspired and in light cooperation with the German model.

The pupils were invited to submit ideas to design and produce a micro chip. In February the jury selected the six best ideas and we invited these teams with a total of 15 pupils to participate in a three-day workshop in March. The pupils learned how to design their own chip (VHDL). Since the workshop they have time until end of June to develop and verify their chip idea. Afterwards their work will be assessed and ordered by its quality. The best work will be selected, synthesized and produced as a chip in a CMOS 0.35µm technology by Austriamicrosystems.


All pupils completing their design will be awarded with nice prices in November 2011. The first price will be awarded (besides the chip production) with iPads for each pupil. For the teams rated at places 2 and 3 we plan to give FPGA development boards, to realize their idea with reconfigurable logic. Places 4 to 6 will get micro-controller evaluation boards, mainly because most ideas are best suited for this platform.

Motic Microscope Camera SFC File Format

The Motic Microscope Camera software stores all images in their proprietary file format with extension ".sfc". Tthis simply contains binary pixel data. It can be viewed with Matlab with the following commands:

% read width and height information
Width  = fread(fid,1,'uint32=>uint32')
Height = fread(fid,1,'uint32=>uint32')
% read the image
% reshape 1xN vector to Width x Height x 3 (RGB) vector
Note that this code was only tested with images directly saved after capture without any edits.

Dienstag, 19. April 2011

EZ-USB Breakout Board

The Cypress (former Anchor Chip) AN2131 EZ-USB microcontroller contains an improved 8051 plus a USB serial interface engine. The internal 8kByte RAM (Code, Data) can be written from a PC via the USB bus to download the firmware to the chip. Therefore no flash or other non-volatile memory is required. Firmware update is as easy as restarting the PC application.

My first project using the EZ-USB microcontroller was the "EZ1" test board in 2001 with two MAX521 8 channel DACs, a MAX127 8 channel 12 bit ADC (both with I²C interface), a RS232 connector and one for the Infineon FingerTip sensor as well as two LEDs. If you don't have JTAG for debugging, two LEDs is the absolute minimum to trace the program execution.


In the meantime I did several other projects using this microcontroller.

The EZ1 board lacks connections for general purpose digital signals (e.g. to control an OLED). Therefore a new board was required. Contrary to the EZ1 it holds the 80 pin version of the microcontroller. All signal pins are connected to pin sockets. Port A is also connected to eight LEDs (with a driver chip).

The new board already proved useful to control an OLED module (ELV ODM100). The image shows the display on the left and the EZ-USB breakout board on the right. The image on the display is only shown partly due to the short exposure time of the camera. The ribbon cable is used to "convert" the pins of the display module to sockets which can be connected with stripped wires to the breakout board (colored wires). ELV offers source code to access the OLED. Only a few changes were necessary to get it working for the 8051. More work helped to speed up the port access and therefore image setup.

Files: Schematic PDF, Eagle Schematic, Eagle Board

Samstag, 16. April 2011

Palm IIIc Disassembled

I've got a Palm IIIc to save from the waste basket. The device is somewhat outdated compared to common smart phones, but its hardware might be used for some project. Therefore I've disassembled it and took some photos for documentation and now posted online.

The most interesting part is probably the main board.
It shows the high voltage inverter for the CCFL background light, the display controller, the DragonBall MC68EZ328 microcontroller, 8 MB GM71VS65163CL DRAM and the 2 MB AM29LV160DB Flash.

How to use this for own projects?
  • The easiest option is to write a program which is then run by normal application by the Palm operating system. It should be possible to use the whole screen with its touch screen for a custom GUI. The real device is then connected via RS232.
  • It would be way more interesting to use one's own firmware for the DragonBall microcontroller. This is quite complicated, because the development tools are only available at the original construction office.

Hello World

This is the first blog post. New posts will follow irregularly.